01Device overview
aebx is a two-board RF front end for USRP1-style motherboards. aebx-rx carries two phase-coherent receive channels with switched preselection and dual-conversion to a common IF; aebx-tx carries one direct-conversion transmit channel that also generates the phase-calibration tone for the receivers. The pair fits one motherboard side (RX and TX connectors), so an ASR34 with two sides provides four coherent receive and two transmit channels.
The design targets direction finding and spectrum monitoring in crowded RF environments, where receiver linearity, preselection and channel-to-channel coherence matter more than raw bandwidth.
02Key features
- Receive coverage 1 MHz – 6 GHz in three bands: direct sampling, 20–300 MHz up-conversion, 0.3–6 GHz down-conversion
- Two phase-coherent RX channels per board on dual mixers with shared LOs
- Six sub-octave preselector filters and a 470 MHz first IF placed clear of reference-clock harmonics
- Switchable LNA for a high-sensitivity or high-linearity setting per band
- 15.5 dB IF gain control in 0.5 dB steps, common to both RF bands
- LO1 out/in for coherence across boards; TX-generated cal tone injected at every RX input
- Same board for ASR34 (AD9862) and ASR35 (AD9963); variants differ by component values only
- All RF components in production; EEPROM board ID for host detection
03Daughterboard specifications
| Feature | aebx-rx | aebx-tx |
|---|---|---|
| Antennas / ports | RF IN1, RF IN2 (SMA); CAL IN, LO1 OUT/IN (U.FL) | TX OUT (SMA); CAL OUT (U.FL) |
| Channels | 2 RX, phase-coherent | 1 TX (I/Q from DAC A/B) |
| Gains | IF DVGA 0–15.5 dB, 0.5 dB step LNA bypass ≈17 dB | Attenuator 0–31.5 dB, 0.5 dB step |
| Bandwidth | 25 MHz (ASR34) 40 MHz (ASR35) | Set by host DAC rate |
| Sensors | LO1 / LO2 lock detect; RF power detector per channel | TX LO lock detect |
| LEDs | LO lock | LO lock, TX active |
| Control | SPI + 16 GPIO + I²C (board ID EEPROM) via motherboard connector | |
04RF specifications
Receive
| Parameter | Band | Value |
|---|---|---|
| Frequency range | B0 direct B1 B2 | 1 MHz – 28 MHz (ASR34) / 40 MHz (ASR35) 20 MHz – 300 MHz 300 MHz – 6 GHz |
| Noise figure | B1 B2 | ≤ 6 dB TARGET ≤ 5 dB TARGET |
| RX IIP3 | B1, B2, LNA on B1, B2, LNA bypassed | ≥ −6 dBm TARGET ≥ +10 dBm TARGET |
| RX IQ imbalance | All | Not applicable: real-IF sampling, no analog I/Q path |
| Image rejection | B2 | Dual conversion, image 940 MHz from RF; value to be measured |
| Input impedance | All | 50 Ω |
| Max input power | All | Limiter-protected; value to be measured |
Transmit
| Parameter | Band | Value |
|---|---|---|
| Frequency range | Direct I/Q low I/Q high | 1 MHz – 50 MHz 50 MHz – 1 GHz 1 GHz – 6 GHz |
| TX power (max) | All | ≥ +5 dBm TARGET +20 dBm with PA option |
| TX IQ imbalance | I/Q bands | Sideband ≈ −50 dBc uncalibrated (modulator typ.) Calibrated value to be measured |
| Output impedance | All | 50 Ω |
05RF performance data
Measured noise figure, IIP3, image rejection and inter-channel phase stability will be published after first-article test.
06Block diagram (aebx-rx, one channel)
flowchart LR
A[RF IN] --> B[Limiter] --> C[Cal inject] --> D[6 GHz LPF] --> E{Band}
E -->|B2 0.3–6 GHz| F[LNA / bypass] --> G[Preselector ×6] --> H[Mixer 1]
E -->|B1 20–300 MHz| I[300 MHz LPF] --> J[LNA / bypass] --> K[Up-converter]
H --> L[IF1 470 MHz]
K --> L
L --> M[Mixer 2 + DVGA] --> N[IF2 filter] --> P{ADC select}
E -->|B0 direct| O[Anti-alias LPF] --> P
P --> Q[ADC driver] --> R[Motherboard ADC]
07Hardware specifications
aebx-rx
- Supply from motherboard +6 V rail, on-board LDOs
- Power ≤ 2 W TARGET
- LO1 synthesizer 53 MHz – 6.8 GHz; fixed LO2
- Shielded RF, LO and IF sections
aebx-tx
- Supply from motherboard rail, on-board LDOs
- Two I/Q modulators plus direct DAC path
- Sub-octave harmonic filter bank
- Optional +20 dBm PA footprint
08Environmental specifications
Components are rated for industrial temperature (−40 °C to +85 °C or wider). System operating range will be stated after qualification.
09Compatibility
| Host | Converter | Sample rate | IF2 | RX bandwidth |
|---|---|---|---|---|
| ASR34 | 2× AD9862 | 64 MSPS | 48 MHz | 25 MHz |
| ASR35 | 2× AD9963 | 100 MSPS | 25 MHz | 40 MHz |
USRP1-style RX/TX connector pinout. Other USRP1-pinout hosts may work with a driver; not validated.
10Phase synchronization
Both channels of a board share LO1 and LO2, so their relative phase is fixed after each tune. Across boards, one board's LO1 drives the other through the LO OUT/IN connectors, and both lock to the motherboard reference clock. The aebx-tx cal tone is split to every RX input, so residual phase and gain differences between all four channels are measured and corrected in the FPGA after each retune.
11Key components
| Function | Part |
|---|---|
| LNA | ADL8122 (10 kHz – 10 GHz) |
| Mixers / IF gain | LTC5566 dual mixer + DVGA ×2, LT5560 |
| Synthesizers | ADF4356, ADF4351 |
| TX modulators | ADL5385 (30 MHz – 2.2 GHz), ADL5375-05 (0.4 – 6 GHz) |
| TX attenuator | HMC624A |
12Schematics and mechanical
USRP-style daughterboard form factor. Schematics and mechanical drawings are available under NDA.
13Certifications and export
- RoHS-compliant component selection
- Export classification pending. Multi-channel coherent receivers of this class may fall under dual-use controls (e.g. 5A001); confirm before export.
14Important notes
- Bandwidth is set by the host converter, not by the RF board.
- TX output ≥ +5 dBm is the base build; higher power requires the PA option.
- All values marked TARGET are pre-measurement and may change.